Computer systems use memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, to store instructions and data that are access by a processor. These memory devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory. In response to the commands and addresses, data is transferred between the system memory and the processor.
FIG. 1 is a functional block diagram of a conventional memory device 100. The memory device 100 in FIG. 1 is an example of a double-data rate (DDR) SDRAM. The memory device 100 is referred to as a double-data-rate device because the data words DQ being transferred to and from the device are transferred at double the rate of a conventional SDRAM, which transfers data at a rate corresponding to the frequency of the applied clock signal. The memory device 100 includes a control logic and command decoder 134 that receives a plurality of command and clock signals over a control bus CONT, typically from an external circuit such as a memory controller (not shown). The command signals include a chip select signal CS#, a write enable signal WE#, a column address strobe signal CAS#, and a row address strobe signal RAS#, while the clock signals include a clock enable signal CKE# and complementary clock signals CLK, CLK#, with the “#” designating a signal as being active LOW. The command signals RAS#, CAS#, and WE# are driven to values corresponding to a particular command, such as a read, write, or auto-refresh command.
In response to the clock signals CLK, CLK#, the command decoder 134 latches and decodes an applied command, and generates a sequence of internal clock and control signals that control the components 102-132 to execute the function of the applied command. The clock enable signal CKE enables clocking of the command decoder 134 by the clock signals CLK, CLK#. The command decoder 134 further includes mode registers 136. Data written to the mode registers 136 are used to set various modes of operation, for example, burst data length, burst type, power-down mode, CAS latency, and the like. The command decoder 134 will generate the appropriate internal clock and control signals based on the modes set by the data stored in the mode registers 136.
The memory device 100 further includes an address register 102 that receives row, column, and bank addresses over an address bus ADDR, with a memory controller (not shown) typically supplying the addresses. The address register 102 receives a row address and a bank address that are applied to a row address multiplexer 104 and bank control logic circuit 106, respectively. The row address multiplexer 104 applies either the row address received from the address register 102 or a refresh row address from a refresh counter 108 to a plurality of row address latch and decoders 110A-D. The bank control logic 106 activates the row address latch and decoder 110A-D corresponding to either the bank address received from the address register 102 or a refresh bank address from the refresh counter 108, and the activated row address latch and decoder latches and decodes the received row address.
In response to the decoded row address, the activated row address latch and decoder 110A-D applies various signals to a corresponding memory bank 112A-D to thereby activate a row of memory cells corresponding to the decoded row address. Each memory bank 112A-D includes a memory-cell array having a plurality of memory cells arranged in rows and columns, and the data stored in the memory cells in the activated row is stored in sense amplifiers in the corresponding memory bank. The row address multiplexer 104 applies the refresh row address from the refresh counter 108 to the decoders 110A-D and the bank control logic circuit 106 uses the refresh bank address from the refresh counter when the memory device 100 operates in an auto-refresh or self-refresh mode of operation in response to an auto- or self-refresh command being applied to the memory device 100, as will be appreciated by those skilled in the art.
A column address is applied on the ADDR bus after the row and bank addresses, and the address register 102 applies the column address to a column address counter and latch 114 which, in turn, latches the column address and applies the latched column address to a plurality of column decoders 116A-D. The bank control logic 106 activates the column decoder 116A-D corresponding to the received bank address, and the activated column decoder decodes the applied column address. Depending on the operating mode of the memory device 100, the column address counter and latch 114 either directly applies the latched column address to the decoders 116A-D, or applies a sequence of column addresses to the decoders starting at the column address provided by the address register 102. In response to the column address from the counter and latch 114, the activated column decoder 116A-D applies decode and control signals to an I/O gating and data masking circuit 118 which, in turn, accesses memory cells corresponding to the decoded column address in the activated row of memory cells in the memory bank 112A-D being accessed.
During data read operations, data being read from the addressed memory cells is coupled through the I/O gating and data masking circuit 118 to a read latch 120. The I/O gating and data masking circuit 118 supplies N bits of data to the read latch 120, which then applies two N/4 bit words to a multiplexer 122. In the embodiment of FIG. 3, the circuit 118 provides 32 bits to the read latch 120 which, in turn, provides four 8 bits words to the multiplexer 122. A data driver 124 sequentially receives the N/4 bit words from the multiplexer 122 and also receives a data strobe signal DQS from a strobe signal generator 126 and a delayed clock signal CLKDEL from the delay-locked loop 123. The DQS signal is used by an external circuit such as a memory controller (not shown) in latching data from the memory device 100 during read operations. In response to the delayed clock signal CLKDEL, the data driver 124 sequentially outputs the received N/4 bits words as a corresponding data word DQ, each data word being output in synchronism with a rising or falling edge of a CLK signal that is applied to clock the memory device 100. The data driver 124 also outputs the data strobe signal DQS having rising and falling edges in synchronism with rising and falling edges of the CLK signal, respectively. Each data word DQ and the data strobe signal DQS collectively define a data bus DATA. The DATA bus also includes masking signals DM0-M for masking write data of data write operations, as will be described in more detail below.
During data write operations, an external circuit such as a memory controller (not shown) applies N/4 bit data words DQ, the strobe signal DQS, and corresponding data masking signals DM on the data bus DATA. A data receiver 128 receives each DQ word and the associated DM signals, and applies these signals to input registers 130 that are clocked by the DQS signal. In response to a rising edge of the DQS signal, the input registers 130 latch a first N/4 bit DQ word and the associated DM signals, and in response to a falling edge of the DQS signal the input registers latch the second N/4 bit DQ word and associated DM signals. The input register 130 provides the two latched N/4 bit DQ words as an N-bit word to a write FIFO and driver 132, which clocks the applied DQ word and DM signals into the write FIFO and driver in response to the DQS signal. The DQ word is clocked out of the write FIFO and driver 132 in response to the CLK signal, and is applied to the I/O gating and masking circuit 118. The I/O gating and masking circuit 118 transfers the DQ word to the addressed memory cells in the accessed bank 112A-D subject to the DM signals, which may be used to selectively mask bits or groups of bits in the DQ words (i.e., in the write data) being written to the addressed memory cells.
As previously described, commands are issued to the memory device 100 in the form of command signals, which are decoded by the command decoder 134 to generate internal clock and control signals to perform the requested operation. FIG. 2 is a command decoding truth table for the memory device 100. The three command signals RAS#, CAS#, and WE# provide eight different commands for the memory device 100. These commands include LOAD MODE, REFRESH, PRECHARGE, BANK ACTIVATE, WRITE, READ, NOP (no operation), and a RESERVED command, which can be used in the future for an additional command. The LOAD MODE command is used to load data into the mode registers 136, which, as previously discussed, is used to set various modes of operation, for example, burst data length, burst type, power-down mode, CAS latency, and the like. The REFRESH command is used to invoke a refresh sequence in the memory banks 112A-D. The PRECHARGE command is used to deactivate or “close” activated, or “open,” memory banks 112A-D. The BANK ACTIVATE command is used to open at least one of the memory banks 112A-D, as selected by a bank address, in preparation for an memory access operation. The WRITE command and the READ command are used to invoke a data write operation and a data read operation, respectively, as previously described. The NOP operation is used to prevent unwanted commands from being registered during idle or wait states of the memory device 100.
The use of the RAS#, CAS#, and WE# signals provides an effective way to issue commands to the memory device 100. However, there are limitations that are inherent with this conventional approach. One such limitation is the maximum number of different possible commands that are provided with the conventional command decoding of the memory device 100. As illustrated above, due to the binary nature of the RAS#, CAS#, and WE# signals, the three command signals provide a maximum decoding of eight different commands. Although eight different commands are sufficient for current technology, it is easy to imagine that in the future there may be the need for more than the eight commands previously described. If additional commands are desired, additional command signals will need to be used. For example, if two additional commands for a total of ten commands are desired, one command could be decoded using the RESERVED command. However, the other additional command would require adding one more signal to the existing three commands signals. With four command signals, there are now potentially sixteen different commands that can be decoded.
Although having additional choices for commands appears to be advantageous, it raises another limitation of the conventional command decoding employed by the memory device 100. That is, increasing the number of command signals to increase the number of different commands that can be decoded, will increase the number of external terminals or “pins” of the memory device 100 that are required to receive the command signals. In the present example, three external terminals are used by the memory device 100 for receiving the RAS#, CAS#, and WE# signals. Having more than the eight possible commands requires at least four external terminals to provide sufficient command decoding. The number can increase to twice that number in light of the development of systems employing differential command signals where each command signal is applied to the memory device as a pair of complementary signals requiring two external terminals.
Currently, the number of external terminals that can be included with a conventionally packaged memory device is reaching its physical limits. The physical dimensions of the memory device package can always be increased to accommodate additional external terminals, however, this solution conflicts with the desirability of creating portable and compact electronic systems. Additionally, adding external terminals increases the number of signal lines that must be used to communicate between a memory controller and the memory device. As applied to memory modules, the additional external terminals of each memory device will require additional conductive traces to be formed on the different layers of the printed circuit board (“PCB”), thus, increasing the complexity of the PCB in design and manufacture. As a result, increasing the number of external terminals in response to the need to accommodate additional command choices is highly undesirable.
Therefore, there is a need for an alternative system and method for command decoding that can be used to provide greater flexibility in increasing the number of commands and/or reducing the number of command signals used in decoding commands.